1) Field of Invention
The invention relates to methods of forming high-density flash memory arrays and the resulting high density flash memory arrays.
2) Description of the Prior Art
In the NOR-type memory cell, the polysilicon memory select gate is connected to a word line, one floating gate-side diffusion is connected to a source line, and the other diffusion is connected to a bit line. Word lines run parallel to the source lines and perpendicular to the bit lines. Better density may be achieved when the source lines are rotated to run parallel to the bit lines, and then combined into single lines. Such high density flash memory arrays, having interchangeable bit lines/source lines between adjacent cells, have been described in previous works such as U.S. Pat. No. 5,654,917 (IBM) to S, Ogura et al, and U.S. Pat. No. 5,278,439 to Yueh Y. Ma: xe2x80x9cSelf-aligned dual-bit split gate (DSG) flash EEPROM cellxe2x80x9d.
Referring to FIG. 1, a schematic of the high density array described in U.S. Pat. No. 5,654,917 is shown. The memory cell is a planar two polysilicon structure, and source and drain regions are interchangeably shared between adjacent cells on the same word line (WL0 or WL1, for example). Read access for this array operates using the current sensing xe2x80x9cdominoxe2x80x9d method or the xe2x80x9cskippy dominoxe2x80x9d method, in which read is limited to serial applications. The bit line to be sensed (one of B0-B4) is always the line that is closest to the selected floating gate. The line on the opposite side of the word gate is then grounded. All other bit lines are pre-charged to the same voltage as the word line high voltage (VDD). Sensing begins when the word line is raised to VDD. In this approach, if the selected cell has a low threshold and the bit line drops below VDDxe2x88x92Vt, then the adjacent cell which shares the same bit line may also start to conduct, depending on its threshold state, and interfere with the bit line signal. Thus, sensing must be completed before the bit line drops beyond VDDxe2x88x92Vt. This stipulation renders sensing of multi-level thresholds difficult, if not impossible.
An array from Yueh Y. Ma""s xe2x80x9cSelf-aligned dual-bit split gate (DSG) flash EEPROM cellxe2x80x9d is shown in FIG. 2A. A cross-section of 2A (2Bxe2x80x942B) is shown in FIG. 2B. The memory cell is a triple polysilicon split gate structure in which the floating gate 22 is polysilicon level 1, the control gate 26 is polysilicon level 2, and the word select gate 30 is polysilicon level 3. Source/drain diffusions 40 are placed every two floating gates apart, thus improving density over the conventional cell, which has separated source and drain regions. Although two floating gates share the same word gate, source and drain regions, read and/or program to a single floating gate is possible because control gates are separated. Above each of the floating gates lies a control gate which controls the voltage of the individual floating gate by capacitance coupling. The control lines run parallel to the source/drain. Some of the disadvantages of the DSG cell are high program voltages of about 12V and also high voltages during read. A high control gate voltage of 12V is required during read operation when one of the floating gates is being accessed in order to mask out the effects from the other floating gate. Adjacent cells which may share the same diffusion or control gate voltages will be effectively disabled from the operation by suppressing the other floating gate with a very low xcx9c0 control gate voltage. The same kind of over-ride and suppress techniques are used during program in order to target a single floating gate cell. In this way, program and read operations can be performed on the high density, self-aligned dual-bit split gate flash/EEPROM cell. However, the highest density ideal memory will be one that not only uses silicon area effectively, but also implements multi-level storage.
In this invention, a fast program, low voltage, ultra-high density, dual-bit, multi-level flash memory is achieved with a three or four-polysilicon split gate sidewall process. The structure and operation of this invention is enabled by the ballistic transistor which provides high electron injection efficiency at low program voltages of 3xcx9c5V. The ballistic transistor is described in the article, xe2x80x9cLow Voltage, Low Current, High speed program step split cell with ballistic direct injection for EEPROM/Flash,xe2x80x9d by S. Ogura et al, IEDM 1998, pg. 987. The cell structure is realized by (i) placing floating gates on both sides of the word gate, and (ii) isolating between the floating gates using a self-aligned isolation scheme which renders the floating gate width equal to the active device width. Third level poly control gates are also formed by the self-alignment method and are shared between memory cells. The control gates enable multi-level storage on each of the floating gates because they can over-ride the coupling between the floating gates and the word line. Key process elements used in this process are:
(i) Disposable sidewall process to fabricate ultra short channel with or without step structure and sidewall floating gate
(ii) Self-aligned filling SiO2 between word gates,
(iii) Control gate polysilicon runs between floating gates on top of and in the direction of the bit line diffusion, perpendicular to the top word gate
Features of the fast program, low voltage, ultra-high density, dual-bit, multi-level flash memory of the present invention include:
1. high density dual-bit cell that can store multi-levels;
2. low current, low voltage programming by ballistic injection;
3. third level control poly gates to over-ride word gate coupling to the floating gate.
A summary of the operating conditions for multi-level storage is given in FIG. 3B. During read, the following conditions need to be met: the voltage of the unselected floating gate within a selected memory cell must be greater than the threshold voltage of the floating gate+source voltage. The word select gate in the floating gate pair is raised to the threshold voltage of the word gate+an override delta of around 0.5V+source voltage (Vtxe2x88x92wl+Voverdrive+Vs). Un-selected floating gates will be disabled by reducing the associated control gates to 0V. Program conditions are: Word line voltage is greater than threshold+an overdrive voltage delta for low current program. Both floating gates in the selected pair are greater than Vtxe2x88x92high+override delta. The floating gate voltages are determined by the voltages of the control gates and the word gates, and their respective coupling ratios. Adjacent floating gates sharing the same word line voltage are disabled by adjusting the control gates only.
Operating conditions of this cell are unique because the cell utilizes the ballistic injection mechanism for fast low voltage program, and two floating gates per word gate with control gates between adjacent cells require additional voltage constraints not found in more conventional one floating gate/one word gate memories. This fast program, low voltage, ultra-high density, dual-bit, multi-level flash memory cell has a smaller density than the DSG cell. Sidewall processing can cut the cell size by more than half. This cell has higher performance. Ballistic injection for program results in faster, low voltage program. Lower control gate voltage is found in this cell. In the DSG cell, floating gate coupling depends mainly on the control gate. In the cell of the present invention, floating gate coupling comes from both the word gate and the control gate. Thus, control gate voltage during program and read can be lower. Bit erase is possible in the inventive memory cell. In DSG, in both cases.of F-N tunneling erase from floating gate to diffusion, or from floating gate to control gate, erase occurs in a column, parallel to the bit line. Erase of a single cell is not possible. However, in the inventive cell, because the coupling is divided more equally between the control gate and the word gate, it is also possible to put a negative voltage on a single word gate, and erase a single bit. The present invention provides faster and better control for multi-level program. Because the ballistic injection has low current program, it is possible to apply autoprogram to this cell This allows better threshold control in less time because there is no need for a separate verification step.
Thus, by a combination of a dual-density cell structure and multi-level storage, a high density memory cell can be made. Furthermore, the high density memories described in this invention have the additional features of fast random access, and low voltage, fast program.